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740 Digitizer
62.5MS/s Digitizer supporting DPP-QDC firmware
64 Channel 12 bit 62.5 MS/s Digitizer supporting DPP-QDC firmware

V1740
64 Channel 12 bit 62.5 MS/s Digitizer
12 bit 62.5 MS/s ADC
64 channels
Two ERNI SMC Dual Row 68pin connectors (32 + 32 channels)
2 Vpp single ended input range (10 Vpp also available)
16-bit programmable DC offset adjustment: ±1 V (±5 V)
Trigger Time stamps
Memory buffer: 192 kS/ch or 1.5 MS/ch, up to 1024 events
FPGA for real-time data processing
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