742 Digitizer
32+2 Channel 12bit 5 GS/s Switched Capacitor Digitizer
16+1 Channel 12bit 5 GS/s Switched Capacitor Digitizer
V1742
32+2 Channel 12bit 5 GS/s Switched Capacitor Digitizer
12 bit @ 5 GS/s, 1-unit wide 6U VME64 module
Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)
1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)
5 GS/s , 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
32 analog input channels on MCX coaxial connectors
2 additional analog inputs (TR0 and TR1):
fast (low latency) trigger
digitizable for high resolution timing (up to 50 ps)
1 Vpp input dynamic range (2 Vpp on request) with programmable DC offset adjustment
Dead-time due to conversion: 110 µs (analog inputs only), 181 µs (TR0, TR1 inputs)
Trigger modes:
External on TRG-IN connector; common to all groups
Fast (Low Latency) on TR0 and TR1 connectors; common to couples of groups
Self-trigger, combinations of channels over-threshold in logic OR; common to couples of groups
Memory buffer options: 128 events/ch; 1024 events/ch
VME64 (VME64X compliant) and Optical Link communication interfaces
Multi-board synchronization features
16 programmable LVDS I/Os
Demo software tools, C and LabVIEW libraries
VX1742
32+2 Channel 12bit 5 GS/s Digitizer
12 bit @ 5 GS/s, 1-unit wide 6U VME64 module
Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)
1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)
5 GS/s, 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
32 analog input channels on MCX coaxial connectors
2 additional analog inputs (TR0 and TR1):
fast (low latency) trigger
digitizable for high resolution timing (up to 50 ps)
1 Vpp input dynamic range (2 Vpp on request) with programmable DC offset adjustment
Dead-time due to conversion: 110 µs (analog inputs only), 181 µs (TR0, TR1 inputs)
Trigger modes:
External on TRG-IN connector; common to all groups
Fast (Low Latency) on TR0 and TR1 connectors; common to couples of groups
Self-trigger, combinations of channels over-threshold in logic OR; common to couples of groups
Memory buffer options: 128 events/ch; 1024 events/ch
VME64 (VME64X compliant) and Optical Link communication interfaces
Multi-board synchronization features
16 programmable LVDS I/Os
Demo software tools, C and LabVIEW libraries
DT5742
16+1 Channel 12 bit 5 GS/s Switched Capacitor Digitizer
12 bit @ 5 GS/s, Desktop module
Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)
1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)
5 GS/s, 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
16 analog input channels on MCX coaxial connectors
1 additional analog input (TR0):
fast (low latency) trigger
digitizable for high resolution timing (up to 50 ps)
1 Vpp input dynamic range (2 Vpp on request) with programmable DC offset adjustment
Dead-time due to conversion: 110 µs (analog inputs only), 181 µs (TR0 input)
Trigger modes:
External on TRG-IN connector; common to all groups
Fast (Low Latency) on TR0 connector; common to all groups
Self-trigger, combinations of channels over-threshold in logic OR; common to all groups
Memory buffer options: 128 events/ch; 1024 events/ch
USB and Optical Link communication interfaces
Demo software tools, C and LabVIEW libraries
N6742
16+1 Channel 12bit 5 GS/s Switched Capacitor Digitizer
12 bit @ 5 GS/s, 1-unit wide NIM module
Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)
1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)
5 GS/s, 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
16 analog input channels on MCX coaxial connectors
1 additional analog input (TR0):
fast (low latency) trigger
digitizable for high resolution timing (up to 50 ps)
1 Vpp input dynamic range (2 Vpp on request) with programmable DC offset adjustment
Dead-time due to conversion: 110 µs (analog inputs only), 181 µs (TR0 input)
Trigger modes:
External on TRG-IN connector; common to all groups
Fast (Low Latency) on TR0 connector; common to all groups
Self-trigger, combinations of channels over-threshold in logic OR; common to all groups
Memory buffer options: 128 events/ch; 1024 events/ch
USB and Optical Link communication interfaces
Demo software tools, C and LabVIEW libraries